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产品 | CDCLVP1102![]() | ||
描述 | The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications. | ||
操作 | 查看详情 | 点击下载 | 立即购买 |
制造商 | 型号 | 分类 | 描述 | 下载 |
---|---|---|---|---|
![]() Weidmuller | 0590280000 | 连接器接线座 - Din 轨道,通道 | term block DK 4qv ts32 BL | |
![]() Weidmuller | 0590260000 | 连接器接线座 - Din 轨道,通道 | term block DK 4qv ts32 PA BG | |
![]() Weidmuller | 0590160000 | 连接器接线座 - Din 轨道,通道 | term dual lvl DK 4Q ts35 PA BG | |
![]() Weidmuller | 0590180000 | 连接器接线座 - Din 轨道,通道 | term dual lvl DK 4Q ts35 PA BU | |
![]() Weidmuller | 0590060000 | 连接器接线座 - Din 轨道,通道 | term dual lvl DK 4Q ts32 PA BG |