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产品 | CDCLVD2104![]() | ||
描述 | The CDCLVD2104 clock buffer distributes two clock inputs (IN0, IN1) to a total of 8 pairs of differential LVDS clock outputs (OUT0, OUT7). Each buffer block consists of one input and 4 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.The CDCLVD2104 is specifically designed for driving 50-transmission lines. If the input is in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin. | ||
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制造商 | 型号 | 分类 | 描述 | 下载 |
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![]() Weidmuller | 0175960000 | 连接器接线座 - Din 轨道,通道 | conn term block w/o spigot PA BG |