The CDCLVP1102 is a highly versatile, low additive jitter buffer that can generate two copies of LVPECL clock outputs from one LVPECL, LVDS, or LVCMOS input for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 10 ps, making the device a perfect choice for use in demanding applications.
|0005060117||连接器刀片式电源连接器 - 触头||term blade female 14-18awg tin|
|0005121102||连接器端子 - 专用连接器||conn female term 14-18awg crimp|
|0005060301||flat blade crimp terminal, series 2176, female, with tin (Sn) plated brass contact, with detent, 14-22 awg (or 18 awg double crimp), reel packaged|
|0005121104||连接器端子 - 专用连接器||conn female term 14-18awg crimp|